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1 ? fn7186.6 el5120, el5220, EL5420 12mhz rail-to-rail input-output op amps the el5120, el5220, and EL5420 are low power, high voltage, rail-to-rail input-output amplifiers. the el5120 contains a single amplifier, the el5220 contains two amplifiers, and the EL5420 contains four amplifiers. operating on supplies ranging from 5v to 15v, while consuming only 500a per ampl ifier, the el5120, el5220, and EL5420 have a bandwidth of 12mhz (-3db). they also provide common mode input ability beyond the supply rails, as well as rail-to-rail output capability. this enables these amplifiers to offer maximum dynamic range at any supply voltage. the el5120, el5220, and EL5420 also feature fast slewing and settling times, as well as a high output drive capability of 30ma (sink and source). these features make these amplifiers ideal for use as voltage reference buffers in thin film transistor liquid crystal displays (tft-lcd). other applications include battery power, portable devices, and anywhere low power consumption is important. the EL5420 is available in the space-saving 14 ld tssop package, the industry-standard 14 ld soic package, as well as the 16 ld qfn package. the el5220 is available in the 8 ld msop package and the 8ld dfn package. the el5120 is available in the 5 ld tsot package. all feature a standard operational amplifier pin out. these amplifiers are specified for operation over the full -40c to +85c temperature range. features ? 12mhz -3db bandwidth ? supply voltage = 4.5v to 16.5v ? low supply current (per amplifier) = 500a ? high slew rate = 10v/s ? unity-gain stable ? beyond the rails input capability ? rail-to-rail output swing ? ultra-small package ? pb-free available (rohs compliant) applications ? tft-lcd drive circuits ? electronics notebooks ? electronics games ? touch-screen displays ? personal communication devices ? personal digital assistants (pda) ? portable instrumentation ? sampling adc amplifiers ? wireless lans ? office automation ? active filters ? adc/dac buffer data sheet march 4, 2009 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2004, 2005, 2007, 2008, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. www.datasheet.net/ datasheet pdf - http://www..co.kr/
2 fn7186.6 march 4, 2009 ordering information part number part marking temp. range (c) package pkg. dwg. # el5120iwt-t7* k -40 to +85 5 ld tsot tape and reel mdp0049 el5120iwt-t7a* k -40 to +85 5 ld tsot tape and reel mdp0049 el5120iwtz-t7* (note) bkaa -40 to +85 5 ld tsot tape and reel (pb-free) mdp0049 el5120iwtz-t7a* (note) bkaa -40 to +85 5 ld tsot tape and reel (pb-free) mdp0049 el5220ilz-t13 *(note) 20z -40 to +85 8 ld dfn tape and reel (pb-free) l8.2x3 el5220cy d -40 to +85 8 ld msop mdp0043 el5220cy-t7 d -40 to +85 8 ld msop tape and reel mdp0043 el5220cy-13 d -40 to +85 8 ld msop tape and reel mdp0043 el5220cyz (note) bbaaa -40 to +85 8 ld msop (pb-free) mdp0043 el5220cyz-t7* (note) bbaaa -40 to +85 8 ld msop tape and reel (pb-free) mdp0043 el5220cyz-t13* (note) bbaaa -40 to +85 8 ld msop tape and reel (pb-free) mdp0043 EL5420cl 5420cl -40 to +85 16 ld qfn mdp0046 EL5420cl-t7 5420cl -40 to +85 16 ld qfn tape and reel mdp0046 EL5420cl-t13 5420cl -40 to +85 16 ld qfn tape and reel mdp0046 EL5420clz (note) 5420clz -40 to +85 16 ld qfn (pb-free) mdp0046 EL5420clz-t7* (note) 5420clz -40 to +85 16 ld qfn tape and reel (pb-free) mdp0046 EL5420clz-t13* (note) 5420clz -40 to +85 16 ld qfn tape and reel (pb-free) mdp0046 EL5420cs 5420cs -40 to +85 14 ld soic mdp0027 EL5420cs-t7 5420cs -40 to +85 14 ld soic tape and reel mdp0027 EL5420cs-t13 5420cs -40 to +85 14 ld soic tape and reel mdp0027 EL5420csz (note) 5420csz -40 to +85 14 ld soic (pb-free) mdp0027 EL5420csz-t7* (note) 5420csz -40 to +85 14 ld soic tape and reel (pb-free) mdp0027 EL5420csz-t13* (note) 5420csz -40 to +85 14 ld soic tape and reel (pb-free) mdp0027 EL5420cr 5420cr -40 to +85 14 ld tssop mdp0044 EL5420cr-t7* 5420cr -40 to +85 14 ld tssop tape and reel mdp0044 EL5420cr-t13* 5420cr -40 to +85 14 ld tssop tape and reel mdp0044 EL5420crz (note) 5420crz -40 to +85 14 ld tssop (pb-free) m14.173 EL5420crz-t7* (note) 5420crz -40 to +85 14 ld tssop tape and reel (pb-free) m14.173 EL5420crz-t13* (note) 5420crz -40 to +85 14 ld tssop tape and reel (pb-free) m14.173 * please refer to tb347 for details on reel specifications. note: these intersil pb-free plastic packa ged products employ special pb-free material sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 termination fi nish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. el5120, el5220, EL5420 www.datasheet.net/ datasheet pdf - http://www..co.kr/
3 fn7186.6 march 4, 2009 pinouts EL5420 (16 ld qfn) top view 1 2 3 5 4 1 2 3 4 8 7 6 5 1 2 3 4 12 11 10 9 5 6 7 8 16 15 14 13 vina- vina+ vs+ vinb+ vinb- voutb voutc vinc- nc vouta voutd nc vind- vind+ vs- vinc+ vs+ vin- vin+ vs- vout vs+ voutb vinb- vinb+ vs- vina+ vina- vouta - + - + - + thermal pad el5220 (8 ld msop) top view el5120 (5 ld tsot) top view 1 2 3 4 14 13 12 11 5 6 7 10 9 8 -+ - + voutd vind- vind+ vs- vinc+ vinc- voutc voutb vinb- vinb+ vs+ vina+ vina- vouta -+ - + EL5420 (14 ld tssop, soic) top view 2 3 4 1 7 6 5 8 vouta vina- vina+ vs- vs+ voutb vinb- vinb+ el5220 (8 ld dfn) top view thermal pad thermal pad connects to vs- thermal pad connects to vs- el5120, el5220, EL5420 www.datasheet.net/ datasheet pdf - http://www..co.kr/
4 fn7186.6 march 4, 2009 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maxi mum ratings (t a = +25c) thermal information supply voltage between v s + and v s - . . . . . . . . . . . . . . . . . . . .+18v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . v s - - 0.5v, v s +0.5v maximum continuous output current . . . . . . . . . . . . . . . . . . . 30ma maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125c thermal resistance (typical) ja (c/w) 5 ld tsot (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . 214 8 ld dfn (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8 ld msop (note 1). . . . . . . . . . . . . . . . . . . . . . . . . 115 16 ld qfn (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . 44 14 ld soic (note 1) . . . . . . . . . . . . . . . . . . . . . . . . 82 14 ld tssop (note 1) . . . . . . . . . . . . . . . . . . . . . . . 93 storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. electrical specifications v s + = +5v, v s - = -5v, r l = 10k and c l = 10pf to 0v, t a = +25c, unless otherwise specified. parameter description conditions min typ max unit input characteristics v os input offset voltage v cm = 0v 2 12 mv tcv os average offset voltage drift (note 3) 5 v/c i b input bias current v cm = 0v 2 50 na r in input impedance 1g c in input capacitance 1.35 pf cmir common-mode input range -5.5 +5.5 v cmrr common-mode rejection ratio for v in from -5.5v to +5.5v 50 70 db a vol open loop gain -4.5v v out + 4.5v 75 95 db output characteristics v ol output swing low i l = -5ma -4.92 -4.85 v v oh output swing high i l = 5ma 4.85 4.92 v i sc short circuit current 120 ma i out output current 30 ma power supply performance psrr power supply rejection ratio v s is moved from 2.25v to 7.75v 60 80 db i s supply current (per amplifier) no load 500 750 a dynamic performance sr slew rate (note 4) -4.0v v out + 4.0v, 20% to 80% 10 v/s t s settling to +0.1% (a v = +1) (a v = +1), v o = 2v step 500 ns bw -3db bandwidth r l = 10k , c l = 10pf 12 mhz gbwp gain-bandwidth product r l = 10k , c l = 10pf 8 mhz el5120, el5220, EL5420 www.datasheet.net/ datasheet pdf - http://www..co.kr/
5 fn7186.6 march 4, 2009 pm phase margin r l = 10k , c l = 10pf 50 cs channel separation f = 5mhz (el5220 and EL5420 only) 75 db notes: 3. measured over operating temperature range. 4. slew rate is measured on rising and falling edges. electrical specifications v s + = +5v, v s - = -5v, r l = 10k and c l = 10pf to 0v, t a = +25c, unless otherwise specified. parameter description conditions min typ max unit electrical specifications v s + = +5v, v s - = 0v, r l = 10k and c l = 10pf to 2.5v, t a = +25c, unless otherwise specified. parameter description conditions min typ max unit input characteristics v os input offset voltage v cm = 2.5v 2 10 mv tcv os average offset voltage drift (note 5) 5 v/c i b input bias current v cm = 2.5v 2 50 na r in input impedance 1g c in input capacitance 1.35 pf cmir common-mode input range -0.5 +5.5 v cmrr common-mode rejection ratio for v in from -0.5v to +5.5v 45 66 db a vol open loop gain 0.5v v out + 4.5v 75 95 db output characteristics v ol output swing low i l = -5ma 80 150 mv v oh output swing high i l = +5ma 4.85 4.92 v i sc short circuit current 120 ma i out output current 30 ma power supply performance psrr power supply rejection ratio v s is moved from 4.5v to 15.5v 60 80 db i s supply current (per amplifier) no load 500 750 a dynamic performance sr slew rate (note 6) 1v v out 4v, 20% to 80% 10 v/s t s settling to +0.1% (a v = +1) (a v = +1), v o = 2v step 500 ns bw -3db bandwidth r l = 10k , c l = 10pf 12 mhz gbwp gain-bandwidth product r l = 10k , c l = 10pf 8 mhz pm phase margin r l = 10k , c l = 10pf 50 cs channel separation f = 5mhz (el5220 and EL5420 only) 75 db notes: 5. measured over operating temperature range. 6. slew rate is measured on rising and falling edges. el5120, el5220, EL5420 www.datasheet.net/ datasheet pdf - http://www..co.kr/
6 fn7186.6 march 4, 2009 electrical specifications v s + = +15v, v s - = 0v, r l = 10k and c l = 10pf to 7.5v, t a = +25c, unless otherwise specified. parameter description conditions min typ max unit input characteristics v os input offset voltage v cm = 7.5v 2 14 mv tcv os average offset voltage drift (note 7) 5 v/c i b input bias current v cm = 7.5v 2 50 na r in input impedance 1g c in input capacitance 1.35 pf cmir common-mode input range -0.5 +15.5 v cmrr common-mode rejection ratio for v in from -0.5v to +15.5v 53 72 db a vol open loop gain 0.5v v out 14.5v 75 95 db output characteristics v ol output swing low i l = -5ma 80 150 mv v oh output swing high i l = +5ma 14.85 14.92 v i sc short circuit current 120 ma i out output current 30 ma power supply performance psrr power supply rejection ratio v s is moved from 4.5v to 15.5v 60 80 db i s supply current (per amplifier) no load 500 750 a dynamic performance sr slew rate (note 8) 1v v out 14v, 20% to 80% 10 v/s t s settling to +0.1% (a v = +1) (a v = +1), v o = 2v step 500 ns bw -3db bandwidth r l = 10k , c l = 10pf 12 mhz gbwp gain-bandwidth product r l = 10k , c l = 10pf 8 mhz pm phase margin r l = 10k , c l = 10pf 50 cs channel separation f = 5mhz (el5220 and EL5420 only) 75 db notes: 7. measured over operating temperature range 8. slew rate is measured on rising and falling edges el5120, el5220, EL5420 www.datasheet.net/ datasheet pdf - http://www..co.kr/
7 fn7186.6 march 4, 2009 typical performance curves figure 1. EL5420 input offset voltage distributi on figure 2. EL5420 input offset voltage drift figure 3. input offset voltage vs temperatur e figure 4. input bias current vs temperature figure 5. output high voltage vs temperature figure 6. output low voltage vs temperature 400 1200 quantity (amplifiers) input offset voltage (mv) 0 -12 1800 1600 800 200 1400 1000 600 -10 -8 -6 -4 -2 -0 2 4 6 8 10 12 v s = 5v t a = +25c typical production distribution input offset voltage drift, tcv os (v/c) 1 3 5 7 9 11 13 15 17 19 21 10 50 quantity (amplifiers) 0 70 30 60 40 20 v s = 5v typical production distribution 0150 0 5 input offset voltage (mv) temperature (c) -5 50 -50 100 10 v s = 5v 0.0 input bias current (na) temperature (c) -2.0 2.0 0 150 50 -50 100 v s = 5v 4.94 4.95 output high voltage (v) 4.93 4.97 0 150 temperature (c) 50 -50 100 4.96 v s = 5v i out = 5ma -4.95 -4.93 output low voltage (v) -4.97 -4.91 0 150 temperature (c) 50 -50 100 -4.92 -4.94 -4.96 v s = 5v i out = -5ma el5120, el5220, EL5420 www.datasheet.net/ datasheet pdf - http://www..co.kr/
8 fn7186.6 march 4, 2009 figure 7. open loop gain vs temperature figure 8. slew rate vs temperature figure 9. EL5420 supply current per amplifier vs temperature figure 10. EL5420 supply current per amplifier vs supply voltage figure 11. open loop gain and phase vs freque ncy figure 12. frequency response for various r l typical performance curves (continued) 80 90 open loop gain (db) 100 0150 temperature (c) 50 -50 100 v s = 5v r l = 10k 0 150 10.30 10.35 slew rate (v/s) temperature (c) 10.25 50 -50 100 10.40 v s = 5v 0.5 0.55 supply current (ma) 0.45 0 150 temperature (c) 50 -50 100 v s = 5v 520 400 600 supply current (a) supply voltage (v) 300 10 0 700 500 15 t a = +25c 10 10k 100m 50 200 frequency (hz) -50 gain (db) phase () 20 -130 -230 100 1k 100k 1m 10m 150 0 100 -30 -80 -180 v s = 5v, t a = +25c r l = 10k to gnd c l = 12pf to gnd phase gain 1m 100m -5 0 magnitude (normalized) (db) frequency (hz) -15 10m 100k 5 -10 c l = 10pf a v = 1 v s = 5v 10k 1k 560 150 el5120, el5220, EL5420 www.datasheet.net/ datasheet pdf - http://www..co.kr/
9 fn7186.6 march 4, 2009 figure 13. frequency response for various c l figure 14. closed loop output impedance vs frequency figure 15. maximum output swing vs fr equency figure 16. cmrr vs frequency figure 17. psrr vs frequency figure 18. inpu t voltage noise spectral density vs frequency typical performance curves (continued) 1m 100m frequency (hz) 10m 100k 0 10 magnitude (normalized) (db) -30 20 -20 -10 r l = 10k a v = 1 v s = 5v 12pf 50pf 100pf 1000pf output impedance ( ) frequency (hz) 10k 100k 0 40 80 120 200 1m 160 10m a v = 1 v s = 5v t a = +25c maximum output swing (v p-p ) frequency (hz) 10k 100k 0 2 4 12 1m 6 10m 8 10 v s = 5v t a = +25c a v = 1 r l = 10k c l = 12pf distortion <1% 100 0 cmrr (db) frequency (hz) 80 60 40 20 1m 10m 10k 100k 1k v s = 5v t a = +25c 100 0 psrr (db) frequency (hz) 80 60 40 20 1m 10m 10k 100k v s = 5v t a = +25c 1k psrr+ psrr- 100 100k 100m 10 100 voltage noise (nv/ hz) frequency (hz) 1 10m 1k 10k 1m 600 el5120, el5220, EL5420 www.datasheet.net/ datasheet pdf - http://www..co.kr/
10 fn7186.6 march 4, 2009 figure 19. total harmonic distortion + noise vs frequency figure 20. channel separation vs frequency response figure 21. small signal overshoot vs load capacitance figure 22. settling time vs step size figure 23. large signal trans ient response figure 24. smal l signal transient response typical performance curves (continued) 1k 10k 100k 0.005 0.008 frequency (hz) thd+ n (%) 0.010 0.001 0.003 v s = 5v r l = 10k a v = 1 v in = 1v rms 0.006 0.009 0.007 0.004 0.002 1k -60 x-talk (db) frequency (hz) -140 -120 -100 -80 1m 6m 10k 100k v s = 5v r l = 10k a v = 1 v in = 220mv rms dual measured channel a to b quad measured channel a to d or b to c other combinations yield improved rejection 10 100 1k load capacitance (pf) overshoot (%) v s = 5v a v = 1 r l = 10k v in = 50mv t a = +25c 50 90 70 30 10 800 -2 2 step size (v) settling time (ns) 600 0 4 200 400 3 1 -3 0 -1 -4 v s = 5v a v = 1 r l = 10k c l = 12pf t a = +25c 0.1% 0.1% v s = 5v t a = +25c a v = 1 r l = 10k c l = 12pf 1v 1s v s = 5v t a = +25c a v = 1 r l = 10k c l = 12pf 50mv 200ns el5120, el5220, EL5420 www.datasheet.net/ datasheet pdf - http://www..co.kr/
11 fn7186.6 march 4, 2009 pin descriptions el5120 el5220 EL5420 pin name pin function equivalent circuit 5 ld tsot 8 ld msop, 8 ld dfn 14 ld tssop, 14 ld soic 16 ld qfn 13, 16 nc no connect in+ amplifier non-inverting input (reference circuit 1) in- amplifier inverting input (reference circuit 1) out amplifier output (reference circuit 2) 3 vin+ amplifier non-inverting input (reference circuit 1) 4 vin- amplifier inverting input (reference circuit 1) 1 vout amplifier output (reference circuit 2) 1 1 15 vouta amplifier a output (reference circuit 2) 2 2 1 vina- amplifier a inverting input (reference circuit 1) 3 3 2 vina+ amplifier a non-inverting input (reference circuit 1) 5 8 4 3 vs+ positive power supply 5 5 4 vinb+ amplifier b non-inverting input (reference circuit 1) 6 6 5 vinb- amplifier b inverting input (reference circuit 1) 7 7 6 voutb amplifier b output (reference circuit 2) 8 7 voutc amplifier c outp ut (reference circuit 2) 9 8 vinc- amplifier c inverti ng input (reference circuit 1) 10 9 vinc+ amplifier c non-invert ing input (reference circuit 1) 2 4 11 10 vs- negative power supply 12 11 vind+ amplifier d non-invert ing input (reference circuit 1) 13 12 vind- amplifier d inverti ng input (reference circuit 1) 14 14 voutd amplifier d ou tput (reference circuit 2) v s+ v s- v s+ gnd v s- circuit 1 circuit 2 el5120, el5220, EL5420 www.datasheet.net/ datasheet pdf - http://www..co.kr/
12 fn7186.6 march 4, 2009 applications information product description the el5120, el5220, and EL5420 voltage feedback amplifiers are fabricated using a high voltage cmos process. they exhibit rail-to-rail input and output capability, they are unity gain stable, and have low power consumption (500a per amplifier). these features make the el5120, el5220, and EL5420 ideal for a wide range of general- purpose applications. connected in voltage follower mode and driving a load of 10k and 12pf, the el5120, el5220, and EL5420 have a -3db bandwidth of 12mhz while maintaining a 10v/s slew rate. the el5120 is a single amplifier, the el5220 is a dual amplifier, and the EL5420 is a quad amplifier. operating voltage, input, and output the el5120, el5220, and EL5420 are specified with a single nominal supply voltage from 5v to 15v or a split supply with its total range from 5v to 15v. correct operation is guaranteed for a supply range of 4.5v to 16.5v. most el5120, el5220, and EL5420 spec ifications are stable over both the full supply range and operating temperatures of -40c to +85c. parameter variations with operating voltage and/or temperature are shown in the typical performance curves. the input common-mode volt age range of the el5120, el5220, and EL5420 extends 500mv beyond the supply rails. the output swings of the el5120, el5220, and EL5420 typically extend to within 80mv of positive and negative supply rails with load currents of 5ma. decreasing load currents will extend the output voltage range even closer to the supply rails. figure 25 shows the input and output waveforms for the device in the unity-gain configuration. operation is from 5v supply with a 10k load connected to gnd. the input is a 10v p-p sinusoid. the output voltage is ap proximately 9.985v p-p . figure 25. operation with rail-to-rail input and output short circuit current limit the el5120, el5220, and EL5420 will limit the short circuit current to 120ma if the output is directly shorted to the positive or the negative supply . if an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. maximum reliability is maintained if the output cont inuous current never exceeds 30ma. this limit is set by the design of the internal metal interconnects. output phase reversal the el5120, el5220, and EL5420 are immune to phase reversal as long as the input voltage is limited from (v s -) -0.5v to (v s +) +0.5v. figure 26 show s a photo of the output of the device with the input voltage driven beyond the supply rails. although the device's out put will not change phase, the input's overvoltage should be avoided. if an input voltage exceeds supply voltage by more than 0.6v, electrostatic protection diodes placed in th e input stage of the device begin to conduct and overvoltage damage could occur. figure 26. operation with beyond-the-rails input power dissipation with the high-output drive capa bility of the el5120, el5220, and EL5420 amplifiers, it is possible to exceed the +125c ?absolute-maximum junction temperature? under certain load current conditions. therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the amplifier to remain in the safe operating area. the maximum power dissipation allowed in a package is determined according to equation 1: where: ?t jmax = maximum junction temperature ?t amax = maximum ambien t temperature ? ja = thermal resistance of the package ?p dmax = maximum power dissipation in the package the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power v s = 5v t a = +25c a v = 1 v in = 10v p-p output input v s = 2.5v t a = +25c a v = 1 v in = 6v p-p 1v 100s 1v p dmax t jmax t amax ? ja -------------------------------------------- - = (eq. 1) el5120, el5220, EL5420 www.datasheet.net/ datasheet pdf - http://www..co.kr/
13 fn7186.6 march 4, 2009 supply voltage, plus the power in the ic due to the loads as shown in equation 2: when sourcing, and: when sinking. where: ? i = 1 to 2 for dual and 1 to 4 for quad ?v s = total supply voltage ?i smax = maximum supply current per amplifier ?v out i = maximum output voltage of the application ?i load i = load current if we set the two p dmax equations equal to each other, we can solve for r load i to avoid device overheat. figure 27 provide a convenient way to se e if the device will overheat. the maximum safe power dissipation can be found graphically, based on the pack age type and the ambient temperature. by using the previo us equation, it is a simple matter to see if p dmax exceeds the device's power derating curves. to ensure proper operati on, it is important to observe the recommended derating curves in figure 27. unused amplifiers it is recommended that any unused amplifiers in a dual and a quad package be configured as a unity gain follower. the inverting input should be direct ly connected to the output and the non-inverting input tied to the ground plane. driving capacitive loads the el5120, el5220, and EL5420 can drive a wide range of capacitive loads. as load capacitance increases, however, the -3db bandwidth of the device will decrease and the peaking will increase. the amplifiers drive 10pf loads in parallel with 10k with just 1.5db of peaking, and 100pf with 6.4db of peaking. if less peaking is desired in these applications, a small series resistor (usually between 5 and 50 ) can be placed in series with the output. however, this will obviously reduce the gain slightly. another method of reducing peaking is to add a ?snubber? circuit at the output. a snubber is a shunt load consisting of a resistor in series with a capacitor. values of 150 and 10nf are typical. the advantage of a snubber is that it does not draw any dc load current or reduce the gain power supply bypassing and printed circuit board layout the el5120, el5220, and EL5420 can provide gain at high frequency. as with any high-frequency device, good printed circuit board layout is necessary for optimum performance. ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. for normal single supply operation, where the vs- pin is connected to ground, a 0.1f ceramic capacitor should be placed from vs+ to pin to vs- pin. a 4.7f tantalum capacitor should then be connected in parallel, placed in the region of the amplifie r. one 4.7f capacitor may be used for multiple devices. this same capacitor combination should be placed at each supply pin to gr ound if split supplies are to be used. p dmax iv s i smax v s + ( v out i ) i load i ? + [] = (eq. 2) p dmax iv s i smax v out i ( v s - ) i load i ? + [] = (eq. 3) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 255075100 150 ambient temperature (c) power dissipation (w) 2.27w ja = 44c/w qfn16 125 85 1.22w 870mw ja = 115c/w msop8 ja = 93c/w tssop14 jedec jesd51-7 high effective thermal conductivity test board 1.08w ja = 82c/w soic14 1.800w ja = 55c/w dfn8 figure 27. package power dissipation vs ambient temperature el5120, el5220, EL5420 www.datasheet.net/ datasheet pdf - http://www..co.kr/
14 fn7186.6 march 4, 2009 el5120, el5220, EL5420 dual flat no-lead plastic package (dfn) // nx (b) section "c-c" 5 (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.15 2x e a b c 0.15 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a m c n-1 12 plane seating c a a3 nx b d2/2 nx k for even terminal/side terminal tip c l e l c c l8.2x3 8 lead dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.32 5,8 d 2.00 bsc - d2 1.50 1.65 1.75 7,8 e 3.00 bsc - e2 1.65 1.80 1.90 7,8 e 0.50 bsc - k0.20 - - - l 0.30 0.40 0.50 8 n 8 2 nd 4 3 rev. 0 6/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389. www.datasheet.net/ datasheet pdf - http://www..co.kr/
15 fn7186.6 march 4, 2009 el5120, el5220, EL5420 small outline package family (so) gauge plane a2 a1 l l1 detail x 4???e seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45? a see detail ??? c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994 www.datasheet.net/ datasheet pdf - http://www..co.kr/
16 fn7186.6 march 4, 2009 el5120, el5220, EL5420 mini so package family (msop) 1 (n/2) (n/2)+1 n plane seating n leads 0.10 c pin #1 i.d. e1 e b detail x 3???e gauge plane see detail "x" c a 0.25 a2 a1 l 0.25 c a b d a m b e c 0.08 c a b m h l1 mdp0043 mini so package family symbol millimeters tolerance notes msop8 msop10 a1.101.10 max. - a1 0.10 0.10 0.05 - a2 0.86 0.86 0.09 - b 0.33 0.23 +0.07/-0.08 - c0.180.18 0.05 - d 3.00 3.00 0.10 1, 3 e4.904.90 0.15 - e1 3.00 3.00 0.10 2, 3 e0.650.50 basic - l0.550.55 0.15 - l1 0.95 0.95 basic - n 8 10 reference - rev. d 2/07 notes: 1. plastic or metal protrusions of 0.15mm maximum per side are not included. 2. plastic interlead protrusions of 0.25mm maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994. www.datasheet.net/ datasheet pdf - http://www..co.kr/
17 fn7186.6 march 4, 2009 el5120, el5220, EL5420 thin shrink small outline package family (tssop) n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail ??? end view detail x a2 0???e gauge plane 0.25 l a1 a l1 seating plane mdp0044 thin shrink small outline package family symbol millimeters tolerance 14 ld 16 ld 20 ld 24 ld 28 ld a 1.20 1.20 1.20 1.20 1.20 max a1 0.10 0.10 0.10 0.10 0.10 0.05 a2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 5.00 6.50 7.80 9.70 0.10 e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference rev. f 2/07 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not include interlead flash or protrusions. interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994. www.datasheet.net/ datasheet pdf - http://www..co.kr/
18 fn7186.6 march 4, 2009 el5120, el5220, EL5420 qfn (quad flat no-lead) package family pin #1 i.d. mark 2 1 3 (n-2) (n-1) n (n/2) 2x 0.075 top view (n/2) ne 2 3 1 pin #1 i.d. (n-2) (n-1) n b l n leads bottom view detail x plane seating n leads c see detail "x" a1 (l) n leads & exposed pad 0.10 side view 0.10 b a m c c b a e 2x 0.075 c d 3 5 7 (e2) (d2) e 0.08 c c (c) a 2 c mdp0046 qfn (quad flat no-lead) package family (compliant to jedec mo-220) symbol millimeters tolerance notes qfn44 qfn3 qfn32 a 0.90 0.90 0.90 0.90 0.10 - a1 0.02 0.02 0.02 0.02 +0.03/-0.02 - b 0.25 0.25 0.23 0.22 0.02 - c 0.20 0.20 0.20 0.20 reference - d 7.00 5.00 8.00 5.00 basic - d2 5.10 3.80 5.80 3.60/2.48 reference 8 e 7.00 7.00 8.00 6.00 basic - e2 5.10 5.80 5.80 4.60/3.40 reference 8 e 0.50 0.50 0.80 0.50 basic - l 0.55 0.40 0.53 0.50 0.05 - n 44 38 32 32 reference 4 nd 11 7 8 7 reference 6 ne 11 12 8 9 reference 5 symbol millimeters toler- ance notes qfn28 qfn2 qfn20 qfn16 a 0.90 0.90 0.90 0.90 0.90 0.10 - a1 0.02 0.02 0.02 0.02 0.02 +0.03/ -0.02 - b 0.25 0.25 0.30 0.25 0.33 0.02 - c 0.20 0.20 0.20 0.20 0.20 reference - d 4.00 4.00 5.00 4.00 4.00 basic - d2 2.65 2.80 3.70 2.70 2.40 reference - e 5.00 5.00 5.00 4.00 4.00 basic - e2 3.65 3.80 3.70 2.70 2.40 reference - e 0.50 0.50 0.65 0.50 0.65 basic - l 0.40 0.40 0.40 0.40 0.60 0.05 - n 28 24 20 20 16 reference 4 nd 6 5 5 5 4 reference 6 ne 8 7 5 5 4 reference 5 rev 11 2/07 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. tiebar view shown is a non-functional feature. 3. bottom-side pin #1 i.d. is a diepad chamfer as shown. 4. n is the total number of terminals on the device. 5. ne is the number of terminal s on the ?e? side of the package (or y-direction). 6. nd is the number of terminals on the ?d? side of the package (or x-direction). nd = (n/2)-ne. 7. inward end of terminal may be squar e or circular in shape with radius (b/2) as shown. 8. if two values are listed, multiple exposed pad options are available. refer to device-specific datasheet. www.datasheet.net/ datasheet pdf - http://www..co.kr/
19 fn7186.6 march 4, 2009 el5120, el5220, EL5420 tsot package family e1 n a d e 4 (n/2) 2 1 e1 0.15 d c 2x 0.25 c 2x n/2 tips e b ddd m d c a-b b nx 6 2 3 5 seating plane 0.10 c nx 1 3 c d 0.15 a-b c 2x a2 a1 h c (l1) l 0.25 4???e gauge plane a mdp0049 tsot package family symbol millimeters tolerance tsot5 tsot6 tsot8 a 1.00 1.00 1.00 max a1 0.05 0.05 0.05 0.05 a2 0.87 0.87 0.87 0.03 b 0.38 0.38 0.29 0.07 c 0.127 0.127 0.127 +0.07/-0.007 d 2.90 2.90 2.90 basic e 2.80 2.80 2.80 basic e1 1.60 1.60 1.60 basic e 0.95 0.95 0.65 basic e1 1.90 1.90 1.95 basic l 0.40 0.40 0.40 0.10 l1 0.60 0.60 0.60 reference ddd 0.20 0.20 0.13 - n 5 6 8 reference rev. b 2/07 notes: 1. plastic or metal protrusions of 0.15mm maximum per side are not included. 2. plastic interlead protrusions of 0.15mm maximum per side are not included. 3. this dimension is measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994. 5. index area - pin #1 i.d. will be located within the indicated zone (tsot6 and tsot8 only). 6. tsot5 version has no center lead (shown as a dashed line). www.datasheet.net/ datasheet pdf - http://www..co.kr/
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7186.6 march 4, 2009 el5120, el5220, EL5420 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m14.173 14 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.195 0.199 4.95 5.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n14 147 0 o 8 o 0 o 8 o - rev. 2 4/06 www.datasheet.net/ datasheet pdf - http://www..co.kr/

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